1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to an improvement of a structure of a memory cell array in a dynamic random access memory with a folded bit line structure.
2. Description of the Prior Art
It has been conventionally well-known that a semiconductor memory device comprises a dynamic random access memory as shown in FIG. 1. Referring to FIG. 1, the dynamic random access memory (DRAM) comprises a memory cell array MA having a plurality of memory cells arranged in a matrix of rows and columns, an address buffer AB receiving an external address signal Ext.ADD for generating internal row addresses A0 to An and internal column addresses B0 to Bm, a row decoder RD for decoding the internal row addresses A0 to An and selecting a single row from the memory cell array MA, a column decoder CD for decoding the internal column addresses and selecting a single or more columns from the memory cell array MA, an (I/O+sense amplifier) block IS for writing and reading information data from and to a memory cell designated by the external address Ext.ADD, and a (preamplifier+input/output buffer) block PB connected between the (I/O+sense amplifier) block IS and a data input/output terminal (not shown) for latching and amplifying data to be written or read.
In the memory cell array in the DRAM having such a structure, a folded bit line structure as shown in FIG. 2 has been conventionally used from the point of view of low noise and relaxing a pitch between sense amplifiers.
Referring to FIG. 2, bit lines 6a, 6b, 6c, 6d, 6e, 6f, 6g and 6h are arranged in parallel with each other. In addition, word lines 7a, 7b, 7c, 7d, 7e, 7f, 7g and 7h are arranged in the direction orthogonal to the bit lines 6a to 6h.
A sense amplifier 14a differentially amplifies signals on a bit line pair 6a and 6b. In the same manner, sense amplifiers 14b, 14c and 14d differentially amplify signals on a bit line pair 6c and 6d, signals on a bit line pair 6e and 6f and signals on a bit line pair 6g and 6h, respectively. Each of the bit lines 6a to 6h is connected to a data input/output bus (not shown in FIG. 2) through a column gate which is responsive to an output of a column decoder to be turned on.
As seen from FIG. 2, memory cells are arranged alternately in pairs on the pairs of bit lines and a memory cell is located only at either one of intersections of the paired bit lines (for example, 6a and 6b) and one word line (for example, 7a). For example, a memory cell (a channel portion 12 of a transfer gate, to be exact) is provided at each intersection of the bit line 6a and the word lines 7c, 7d, 7g and 7h. In addition, a memory cell (a channel portion 12 of a transfer gate in the memory cell, to be exact) is provided at each intersection of the bit line 6b and the word lines 7a, 7b, 7e and 7f.
Furthermore, memory cells (channels 12) are provided at intersection of a single word line (for example, 7a) and bit lines (for example, 6b, 6d, 6f and 6h) every other bit line. 2-bit memory cells connected to the same bit line (for example, 6a) and adjacent to each other are connected to a bit line (for example, 6a) through contact holes 10.
In the above described structure, when a single word line (for example, 7a) is selected, a memory cell connected to either one bit line (for example, 6b) of the paired bit lines is selected.
1-bit memory cell region 20 shown in FIG. 2 is specifically illustrated in FIGS. 3 and 4. FIG. 3 is a plan view of the 1-bit memory cell region, and FIG. 4 is a cross sectional view taken along a line 4--4 shown in FIG. 3, wherein a memory cell of a planar type capacitor is shown by way of example. A single memory cell comprises a single transfer gate and a single capacitor. Referring to FIGS. 3 and 4, a transfer gate comprises a word line 7e and diffusion layers 21 and 22. The diffusion layer (a source region of the transfer gate) 22 is connected to a bit line 6d through a contact hole 10. The capacitor portion comprises a cell plate 3 serving as one electrode of the capacitor, the diffusion layer 21 serving as a storage node in which information is stored and an insulating film between the diffusion layer 21 and the cell plate 3. A channel portion 12 of the transfer gate is located at an intersection of the word line 7e and the bit line 6d. A word line 7d crosses over the cell plate 3 of the memory cell connected to the bit line 6d.
As seen from FIGS. 2 to 4, in the conventional folded bit line structure, two word lines are provided in a 1-bit memory cell region.
When the memory cell capacitor 21 (or storage node) stores information charge, the memory cell capacitor 21 is charged to be a power-supply potential or a ground potential. Thus, by determining whether the memory cell capacitor 21 is charged to be a power-supply potential or a ground potential, it can be known whether the selected memory cell capacitor 21 stores information "0" or "1".
An operation for reading out information stored in the memory cell capacitor 21 is generally performed as follows.
All of the bit lines 6 (in the following description, when bit lines are generically referred to, the attached alphabets are omitted. It is the same with sense amplifiers and word lines) are precharged to be a precharge potential which is, in general, a half of the power-supply potential. A memory cycle is then started, so that the internal row addresses A0 to An are generated in response to the external address Ext.ADD. The internal row addresses A0 to An are decoded by the row decoder RD, so that a corresponding word line is selected, and a potential on the selected word line is increased. In order to simplify the explanation, it is assumed that the word line 7d shown in FIG. 2 is selected. When a potential on the word line 7d is increased, a channel region 12 formed under the word line 7d is rendered conductive, so that the memory cell capacitors connected to the channel portions which are rendered conductive are connected to the bit lines 6a, 6c, 6e and 6g, respectively. At that time, a potential on a bit line connected to the memory cell capacitor which is charged to be a power-supply potential, of the bit lines 6a, 6c, 6e and 6g is shifted to a potential higher than the precharge potential, and a potential on a bit line connected to a memory cell capacitor which is charged to be a ground potential is shifted to a potential lower than the precharge potential. On the other hand, potentials on the remaining bit lines 6b, 6d, 6f and 6h remain at the precharge potential. Thus, one bit line of a bit line pair connected to a single sense amplifier 14 is at the precharge potential, and the other bit line is at a potential which is higher or lower than the precharge potential. Then, when the sense amplifier 14 is activated, the potential difference between the bit line pair is differentially amplified. Finally, a single column (a pair of bit lines) is selected by the column decoder CD in response to the internal column addresses from the address buffer AB, so that a signal amplified by the sense amplifier 14 is transmitted to a data bus. Thus, it follows that information stored in a memory cell designated by the external address Ext.ADD is read out. After the word line 7d is selected, the potentials on the bit lines 6a, 6c, 6e and 6g are compared with the precharge potentials on the bit lines 6b, 6d, 6f and 6h which are paired with the bit lines 6a, 6c, 6e and 6g, respectively, whereby information stored in the memory cell capacitor is detected. More specifically, it is determined whether the potentials on the bit lines 6a, 6c, 6e and 6g are higher or lower than the precharge potentials, whereby information stored in the memory cell capacitor is detected.
In such a semiconductor memory device with a folded bit line structure, since a pair of bit lines connected to a single sense amplifier extends adjacent to and in parallel with each other in the same direction, coupling noise received from a semiconductor substrate, a cell plate and/or a word line appears as a common mode noise in each bit line pair. As a result, the common mode noises which appear in the bit line pair are cancelled each other. Therefore, a sense amplifier connected to a bit line pair is not affected by noise, so that a malfunction due to noise does not occur easily.
Furthermore, as can be seen best from FIG. 2, since a pitch for arrangement between sense amplifiers is relaxed to a pitch of 2-bit memory cells, a design rule for a sense amplifier can be easily accommodated into a design rule for a memory cell array.
However, in the conventional semiconductor memory device with a folded bit line structure, bit lines are arranged adjacent to and in parallel with each other, so that one bit line 6 and two word lines 7 are arranged within a 1-bit memory cell region, as shown in FIGS. 2 to 4. Thus, if it is desired to decrease the plane area of a memory cell array for high integration, the area of the 1-bit memory cell should be decreased. In this case, it is necessary that the two word lines are strictly defined to be arranged in parallel with each other within the 1-bit memory cell region. Therefore, high resolution is required in, for example, a photolithography apparatus, so that the price of the apparatus is raised. In addition, a margin for offset of patterns of the word lines is decreased, so that it becomes difficult to manufacture the apparatus.
The prior art of proposing an improvement of a cell array with a folded bit line structure is described in (1) an article by T. Matsumura, entitled "MEMORY ARRAYS FOR HIGH DENSITY DRAM", 1985 IECE Japan, Semiconductor Material Section, National Conference, Proceeding, 1985, P. 2-131, and (2) an article by A.H. Shah et al., entitled "A 4Mb DRAM with Cross Point Trench Transistor Cell", IEEE ISSCC Digest of Technical Papers, 1986, pp. 268-269 and 369.
The first prior art discloses an array structure in which a memory cell array is divided into a plurality of sub-arrays in the direction of bit lines, pass bit lines (bit lines each comprising only an interconnection layer) formed of an interconnection of a different level from that of the bit lines are formed in each of the sub-arrays, and the pass bit lines and the bit lines in the adjacent sub-arrays are connected to each other not to have intersecting portions. In this structure, sense amplifiers are provided on both sides of the sub-arrays. However, it becomes difficult to provide symmetrically the sense amplifiers on both sides of the sub-arrays and to form the same using a symmetrical circuit structure, which presents a problem in, for example, a layout. Further, in this structure, a pass bit line and a bit line are formed of different levels of interconnections, so that an extra interconnection layer is needed and an additional process for the layer is required.
The second prior art discloses a DRAM using Double-Ended Adaptive Folded bit line scheme in which a memory cell array is divided into sub-arrays, a pass word line region and a pass bit line region are removed, memory cells are provided at intersections of the word lines and the bit lines, a bit line connected to the selected memory cell is connected to a different global bit line by a segment select, and 2-bit information is detected every one bit by sense amplifiers provided on both sides of the array. In this structure, a reference bit line is selected by a section select. However, in order to connect the bit line to the global bit line, two switches, that is, the section select and the segment select must be operated, so that a structure and an operation of the cell array are complicated.